The present invention relates to a method and/or architecture for refreshing a memory device generally and, more particularly, to a method and/or architecture for reducing the power consumption for memory devices in refresh operations.
Data (i.e., a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d) is stored in a 1T memory cell as a voltage level. A xe2x80x9c1xe2x80x9d can be stored as a high voltage level which can decrease due to leakage. A xe2x80x9c0xe2x80x9d can be stored as a voltage level of zero volts which can increase due to leakage. Because of leakage, the 1T memory cell uses a periodic refresh to maintain the detected voltage level stored in the cell.
A refresh operation of a memory chip involves a wordline activation that, together with a sensing operation, restores the data stored in the memory cell. When the chip is in an active mode, the current used for refreshing the chip is typically not significant. However, when the chip is in a standby mode, the current used for refreshing can be more important. For example, applications that rely on battery power benefit from low standby current. The growing mobile market has led to a demand for memory devices with a low power standby mode.
Prior dynamic random access memories (DRAMs) refresh all of the memory cells. However, some applications do not need to maintain the data in all of the memory cells during a power down mode or standby mode (i.e., a reduced power mode). Specifically, in battery powered portable terminals (e.g., portable telephones), in many cases, if only some portion of the total memory array has data to be retained in a reduced power mode, all memory cell state information other than that portion need not be retained when in such a mode. Therefore, the current used for refreshing the memory array during the standby mode can be reduced by refreshing only the memory cells containing data to be retained.
However, since conventional dynamic semiconductor memory devices are configured to refresh all the memory cells, reducing the power consumption further (e.g., several hundred microamperes) in the standby mode has been difficult. Because the power consumption in the standby mode can directly affect the continuous standby time, for example, reducing the power consumption in the standby mode can be very important.
Referring to FIG. 1, a conventional memory device 10 is shown. The memory device 10 is similar to one disclosed in U.S. Pat. No. 6,215,714. The memory device 10 has a command decoder 12, an address buffer 14, a refresh control circuit 16, a refresh address register 18, an oscillator 20, a frequency divider 21, a refresh address counter 22, an array control circuit 24, a memory array 26, a selector 28, a selector 30, and an address latch 32. The memory device 10 can refresh all or part of the memory array 26. The device 10 supports partial or full array refresh by programming the refresh address register 18 with the portion of the memory array 26 to be refreshed. The refresh address register 18 controls the higher order bits of the refresh addresses. For example, to refresh half of the memory array 26, the most significant bit is fixed to a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d and the rest of the bits generated by the refresh address counter 22 are cycled through for refresh.
When fewer wordlines are refreshed, the refresh rate does not need to be as fast as when the entire array 26 is refreshed. The frequency divider 21 is configured to reduce the refresh rate in response to a signal from the refresh address register to save standby current. The minimum frequency with which a refresh cycle occurs can be determined by dividing the number of wordlines connecting the memory cells to be refreshed by the memory cell retention time.
The memory array 26 is divided into four quadrants. During a normal (e.g., read or write) operation, a wordline is activated in only one quadrant. However, during a refresh operation, one wordline in each of the four quadrants is activated. During such a refresh cycle, the periphery array circuits of all four quadrants are activated and the refresh address counter (RAC) 22 can select the wordline to activate. The RAC 22 can then be incremented for the next refresh cycle.
A disadvantage of the conventional approach is that the periphery array circuits of all four quadrants are activated when less than the full array 26 requires refreshing. Also, additional circuits (e.g., selector 28) are needed for controlling the higher order address bits.
It would be desirable to reduce the power consumption for battery powered portable terminals and various other appliances that use dynamic semiconductor memory devices.
The present invention concerns a method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for reducing the power consumption of memory devices during background operations, such as memory cell refresh operations, that may (i) reduce standby power requirements of a memory device, (ii) refresh one or more sections of a memory array, (iii) activate the support circuits for sections being refreshed, (iv) leave inactive the support circuits for sections not being refreshed and/or (v) perform parity checking and/or housekeeping operations on one or more sections of a memory array.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
FIG. 1 is a block diagram of a conventional memory device;
FIG. 2 is a block diagram of a memory device in accordance with a preferred embodiment of the present invention;
FIG. 3 is a more detailed block diagram of a memory device in accordance with a preferred embodiment of the present invention;
FIG. 4 is a block diagram of a memory array section of FIG. 3;
FIG. 5 is a more detailed block diagram of a memory array section of FIG. 4;
FIG. 6 is a more detailed block diagram of an array control circuit of FIG. 3; and
FIG. 7 is a block diagram of an alternative embodiment of the present invention.